Random Zero Vector Distribution PWM Algorithm for Direct Torque Control of Induction Motor Drive for Noise Reduction

The basic direct torque control algorithm gives large ripples in torque, flux and current in steady state, which results in acoustical noise and incorrect speed estimations. The conventional SVPWM algorithm gives good performance for control of induction motor drive, but it produces more acoustical noise resulting in increased total harmonics distortion. The random pulse width modulation (RPWM) techniques have become an established means for mitigation of undesirable side effects in adjustable speed ac drives in particular. Hence, to minimize these anomalies of the drive, this paper presents a random zero vector distribution (RZVDPWM) algorithm for direct torque controlled induction motor drive. The proposed random zero vector distribution PWM (RZVDPWM) algorithm distributes the zero state time between the two zero voltage vectors. To validate the proposed PWM algorithm, simulation studies have been carried out and results are presented and compared. From the results, it can be observed that the proposed RZVDPWM algorithm gives reduced acoustical noise when compared with space vector pulse width modulation (SVPWM) algorithm

Space Vector Based Hybrid Random PWM Algorithm for DTC-IM Drive To Achieve Superior Waveform Quality

This paper presents a simplified space vector based hybrid random pulsewidth modulation algorithm for direct torque controlled induction motor drive to achieve superior waveform quality and reduced acoustical noise and harmonic distortion. To reduce the complexity involved in the conventional space vector approach, the proposed pulsewidth modulation (PWM) algorithm uses instantaneous sampled reference phase voltages to calculate the actual switching times of the devices. The proposed PWM algorithm modifies the time duration of application of vector V0 (000) by using a factor. By changing the value of this factor many switching sequences can be derived. The proposed PWM algorithm uses 0127, 012 and 721 switching sequences when value takes 0.5, 1 and 0 respectively. In order to achieve superior waveform quality, the harmonic analysis of these sequences is carried out using the notion of stator flux ripple and expressions are derived for mean square flux ripple in terms of imaginary switching times and modulation index. By comparing the instantaneous ripple values in each sampling time interval, the suitable sequence is selected that results in minimum current ripple. Thus, the proposed algorithm gives reduced harmonic distortion when compared with the SVPWM algorithm. As the zero state time is varied randomly according to the operating sequence, randomization effect will occur, which results in reduced dominating harmonics and hence acoustical noise when compared with the SVPWM algorithm. The simulation results validate the proposed algorithm

Space Vector Based Dual Zero-Vector Random Centered Distribution Pwm Algorithm for Direct Torque Control of Induction Motor Drive For Reduced Acoustical Noise

The direct torque control (DTC) technique has been recognized as the viable solution to achieve precise and quick torque response but it suffers from few drawbacks such as high ripple in torque, flux and stator current resulting in increased vibrations and acoustic noise. The conventional SVPWM algorithm gives good performance for control of induction motor drive, but it also produces considerable acoustical noise resulting in increased total harmonics distortion. The deterministic pulse width-modulation (PWM) method adopted in induction-motor drives causes Acoustical noise due to the switching frequency. This paper presents a novel dual zero-vector random centered distribution PWM algorithm for direct torque controlled induction motor drive. The proposed PWM algorithm uses two zero voltage vectors. When the operating modulation index is less than the critical modulation index, the proposed PWM algorithm uses V0 (000) as zero voltage vector. Otherwise, when the operating modulation index is greater than the critical modulation index, the proposed PWM algorithm uses V7 (111) as zero voltage vector. To verify the proposed PWM algorithm, a numerical simulation studies have been carried out and results are presented and compared with classical SVPWM algorithm. The simulation results confirm the effectiveness of the proposed DZRCDPWM algorithm for the considered drive. Key words: DTC, DZRCDPWM, RPWM, SVPWM, Acoustic noise

Robustness Study of Fractional Order PID Controller Optimized by Particle Swarm Optimization in AVR System

In this paper a novel design method for determining fractional order PID (PIλDµ) controller parameters of an AVR system using particle swarm optimization algorithm is presented. This paper presents how to employ the particle swarm optimization to seek efficiently the optimal parameters of PIλDµ controller. The robustness study is made for this controller against parameter variation of AVR system. This work has been simulated in MATLAB environment with FOMCON (Fractional Order Modeling and Control) tool box.The proposed PSOPIλDµ controller has superior performance and robust compared to GA tuned PIλDµ controller. The results are also compared with PSO tuned PID controller

Performance Enhancement of MIMO MC-CDMA System employing Cylically Rotated Complete Complementary Codes

Wireless communication needs very high data rate and throughput in order to meet increasing demand for multimedia applications. MC-CDMA technique along with multiple input multiple output (MIMO) technique is used to increase data rate and to reduce the channel impairments. Spreading code plays a major role in CDMA technique, Cyclically rotated complete complementary codes (CRCCCs) are used for spreading which have perfect auto-correlation and cross correlation properties. Bit error rate (BER) can be reduced and have other advantages like high data rate, high throughput, reduced inter symbol interference (ISI) and multiple access interference (MAI). MIMO MC-CDMA system employing CRCCCs is designed and simulation results are shown. DOI: 10.17762/ijritcc2321-8169.150614

Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature.publishedVersio

Design and Implementation of Density Sensor for Liquids using Fiber Bragg Grating Sensor

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Fault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGA

Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.publishedVersio

Design and Fabrication of Liquid Pressure Sensor using FBG Sensor through Seesaw Hinge Mechanism

Pressure sensors are used in various industrial applications assisting in preventing unintended disasters. This paper presents the design and fabrication of a novel Seesaw device incorporating a diaphragm and Fiber Bragg Grating (FBG) sensor to measure the pressure of liquids. The designed sensor has been tested in a static water column. The proposed design enables the user to easily make and modify the diaphragm based on the required pressure range without interfering with the FBG sensor. The developed pressure sensor produces improved accuracy and sensitivity to applied liquid pressure in both low and high-pressure ranges without requiring sophisticated sensor construction. A finite element analysis has been performed on the diaphragm and on the entire structure at 10 bar pressure. The deformation of the diaphragm is comparable to theoretical deformation levels. A copper diaphragm with a thickness of 0.25 mm is used in the experiments. All experiments are performed in the elastic region of the diaphragm. The sensor’s sensitivity as 19.244 nm/MPa with the linearity of 99.64% is obtained based on the experiments. Also, the proposed sensor’s performance is compared with recently reported pressure sensors.publishedVersio

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

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